1. Field of the Invention
The present invention relates to a semiconductor memory device and method of transferring data thereof. More specifically, the present invention relates to a semiconductor memory device and method of transferring data thereof, wherein at least one data group, which have to be output first thing, among a N number of data groups that are prefetched from a memory cells array in a N-bit prefetch type, are transferred to the outside faster than the remaining groups.
2. Discussion of Related Art
Generally, a data I/O operation of a synchronous semiconductor memory device is executed in synchronism with an internal clock signal that is generated based on an external clock signal. This type of synchronous semiconductor memory device may include SDR (Single Data Rate) SDRAM (Synchronous Dynamic Random Access Memory), DDR (Double Data Rate) SDRAM, DDR2 SDRAM and DDR3 SDRAM, and the like. In the SDR SDRAM, 1-bit data are prefetched from memory cells, and then output to a DQ (input/output) pad every clock cycle. In the DDR SDRAM, 2-bit data are prefetched from memory cells, and then output to a DQ pad on a clock cycle basis. In the DDR2 SDRAM, 4-bit data are prefetched from memory cells, and then output to a DQ pad on a clock cycle basis. In the DDR3 SDRAM, 8-bit data are prefetched from memory cells, and then output to a DQ pad on a clock cycle basis. Therefore, data processing speed of the DDR2 SDRAM device is faster than that of the DDR SDRAM device, and the data processing speed of DDR3 SDRAM device is faster than that of the DDR2 SDRAM device.
Of them, the DDR2 SDRAM generally uses a 4-bit prefetch scheme. In the 4-bit prefetch scheme, four data groups are prefetched from memory cells in a parallel way based on one read command, and the prefetched four data groups are output through the same DQ pad during 2 clock cycles. In this above example, the number of the data groups is determined according to a data width. For example, if the data width is ×16 and the SDRAM has a 4-bit prefetch scheme, four data groups Q0, Q1, Q2 and Q3 each consisting of sixteen data bits are output from the memory cells to the outside through the DQ pad, as shown in FIG. 1.
FIG. 1 is a timing diagram showing that data read from memory cells in a read operation of a semiconductor memory device are output to the DQ pad through data amplifiers, global I/O buses GIO_Q0<0:15>, GIO_Q1<0:15>, GIO_Q2<0:15> and GIO_Q3<0:15>, and read latch circuits, read multiplexers, and read drivers. At this time, the aforementioned data amplifiers, the read latch circuits, the read multiplexers, and the read drivers are used for a data output path, and are generally well known to those skilled in the art. Thus, detailed description thereof will be omitted for simplicity.
In addition, FIG. 1 shows that the data width of the global I/O bus disposed between the data amplifiers and the read latch circuits is ×16, and the mode is the 4-bit prefetch type. Accordingly, four data groups Q0, Q1, Q2 and Q3 each consisting of sixteen data bits are loaded onto the global I/O buses GIO_Q0<0:15>, GIO_Q1<0:15>, GIO_Q2<0:15> and GIO_Q3<0:15> in which the data width is a total of 16×4=64 bits, respectively.
Furthermore, although not shown in FIG. 1, the read multiplexers output the four data groups Q0, Q1, Q2 and Q3 to the DQ pad in a serial way using lower 2-bit column addresses CA<0:1> in order of the output in accordance with specification defined in JEDEC.
That is, if the column addresses CA<0> and CA<1> are 00, the data groups are output in order of Q0, Q1, Q2 and Q3. If the column addresses CA<0> and CA<1> are 01, the data groups are output in order of Q1, Q2, Q3 and Q0. If the column addresses CA<0> and CA<1> are 10, the data groups are output in order of Q2, Q3, Q0 and Q1. If the column addresses CA<0> and CA<1> are 11, the data groups are output in order of Q3, Q0, Q1 and Q2.
As described above, when a read command RD is input, the output sequence of four data groups that are prefetched in the 4-bit prefetch type is previously determined according to the column addresses CA<0:1>. Technology for improving the output speed of data groups, however, has not yet been developed.